This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-296826, filed Sep. 28, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor integrated circuit and more particularly to a semiconductor integrated circuit used in a buffer circuit of a semiconductor memory which is operated according to a high frequency clock.
2. Description of the Related Art
Recently, the processing capability of computers has been highly enhanced and the study of semiconductor memory devices which can be operated at high speed is being actively pursued. Further, the frequency of a signal transferred between the semiconductor memory which can be operated at high speed and a controller for controlling the semiconductor memory is enhanced and the amplitude thereof is reduced. Therefore, it becomes important to study how to realize an output level and output timing of an output buffer for outputting a signal from the semiconductor memory in accordance with the design.
A conventional output buffer is explained with reference to FIG. 1A. FIG. 1A is a circuit diagram showing an open-drain type output buffer using MOS transistors.
As shown in FIG. 1A, an output buffer 10 includes n-channel MOS transistors 11, 12 and capacitor element 13. The MOS transistor 11 has a gate connected to a node A0, a source and a drain connected to an output node OUT0 of the output buffer 10. The MOS transistor 12 has a gate connected to an input node IN0, a source connected to a ground potential and a drain connected to the source of the MOS transistor 11. The capacitor element 13 has one end connected to the gate of the MOS transistor 11 and the other end connected to the ground potential. The node A0 is applied with voltage V1.
The output node OUT0 of the output buffer 10 is connected to one end of a load element 14 and the other end of the load element is connected to a power supply potential V2. A capacitor 15 is a mirror capacitor parasitically existing between the gate and drain of the MOS transistor 11.
Generally, a semiconductor integrated circuit includes a plurality of output buffers having the same construction as the output buffer 10. The plurality of output buffers output data items independently held therein at the same timing. The semiconductor integrated circuit is explained with reference to FIG. 1B. FIG. 1B is a block diagram showing the semiconductor integrated circuit.
As shown in FIG. 1B, the semiconductor integrated circuit includes seven output buffers 10-0 to 10-6 with the same construction as that shown in FIG. 1A. Nodes A0-0 to A0-6, output nodes OUT0-0 to OUT0-6 and input nodes IN0-0 to IN0-6 of the output buffers 10-0 to 10-6 respectively correspond to the node A0, output node OUT0 and input node IN0 shown in FIG. 1A. The nodes A0-0 to A0-6 are commonly connected. The commonly connected node AA0 is applied with voltage V1. Further, the output nodes OUT0-0 to OUT0-6 are respectively connected to one-side ends of load elements 14-0 to 14-6. The other ends of the load elements 14-0 to 14-6 are connected to a power supply voltage V2. Further, independent switching signals are input to the input nodes IN0-0 to IN0-6.
A semiconductor integrated circuit according to an aspect of the present invention comprises a first MOS transistor having a drain connected to an output terminal, a gate and a source, the gate of the first MOS transistor being applied with voltage not lower than a threshold voltage of the first MOS transistor; a second MOS transistor having a gate supplied with a switching signal used for controlling an output level of the output terminal, a drain connected to the source of the first MOS transistor and a source, the second MOS transistor having the same conductivity type as the first MOS transistor; a first capacitor having one electrode connected to the gate of the first MOS transistor and the other electrode connected to a first node whose potential changes in a complementary fashion with respect to the drain potential of the first MOS transistor, the first capacitor functioning to cancel out an influence, caused by the coupling of the mirror capacitor existing between the gate and drain of the first MOS transistor, affecting the gate potential of the first MOS transistor; and a first inverter having an input terminal connected to the gate of said second MOS transistor and an output terminal connected to the other electrode of the first capacitor.